. GENERAL SPECIFICATIONS
Bandwidth= around 580hz
Chiprate : 300/second (a "chip" is here a "bit" from the point of view of the modulation)
Bits rate (after pseudo WHP inverse transform) : 37.5 per second in CHIP64 and 21.09 in CHIP128
Speed (words) : 48 wpm in capital letters to 68 wpm in small letters (average in CHIP64)
27 wpm in capital letters to 38 wpm in small letters (average in CHIP128)
Modulation : DBPSK
A "block" is composed of 64 chips in Chip64 and 128 in Chip128. A block corresponds to a code on 8 bits in Chip64 and 9 bits in Chip128. The block is obtained from the code, by a WHP transform "Walsh-Hadamard-Porcino", so as:
* to give a good autocorrelation quality necessary for the "block" synchronization, using an "m-sequence"
* a weak intercorrelation between codes to distinguish them, using a Walsh-Hadamard transform.
In Chip64, for the codes between 0 and 127, it will be used the m-sequence[6,5,2,1] for odd codes and the m-sequence[6,5] for the even codes.
In Chip128, for the codes between 0 and 255, it will be used the m-sequence[7,3,2,1] for odd codes and the m-sequence[7,3] for the even codes.
Reception mode : indifferent (LSB or USB)
Character set : ASCII characters + almost all ANSI extended characters + an error reset character (« Varicode » characters)
Shape of pulse : raised cosine
Synchronization : automatic using the signal
Correction code : the use of the WHP transform is equivalent to a a powerful "block" coding type
Convolution code : no,
Interleaving : no
Drift tolerance : 15 Hz/minute (+/- depending on signal level)
Pmean/Ppeak : 0.79
Lowest S/N : - 8 dB